PIC18F45J10 |
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CONFIG1L (address:0x007FF8, mask:0xE1) |
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WDTEN -- Watchdog Timer Enable bit |
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WDTEN = OFF |
0xFE |
WDT disabled (control is placed on SWDTEN bit). |
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WDTEN = ON |
0xFF |
WDT enabled. |
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STVREN -- Stack Overflow/Underflow Reset Enable bit |
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STVREN = OFF |
0xDF |
Reset on stack overflow/underflow disabled. |
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STVREN = ON |
0xFF |
Reset on stack overflow/underflow enabled. |
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XINST -- Extended Instruction Set Enable bit |
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XINST = OFF |
0xBF |
Instruction set extension and Indexed Addressing mode disabled (Legacy mode). |
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XINST = ON |
0xFF |
Instruction set extension and Indexed Addressing mode enabled. |
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DEBUG -- Background Debugger Enable bit |
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DEBUG = ON |
0x7F |
Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug. |
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DEBUG = OFF |
0xFF |
Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins. |
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CONFIG1H (address:0x007FF9, mask:0xF4) |
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CP0 -- Code Protection bit |
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CP0 = ON |
0xFB |
Program memory is code-protected. |
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CP0 = OFF |
0xFF |
Program memory is not code-protected. |
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CONFIG2L (address:0x007FFA, mask:0xC7) |
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FOSC -- Oscillator Selection bits |
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FOSC = HS |
0xFC |
HS oscillator. |
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FOSC = HSPLL |
0xFD |
HS oscillator, PLL enabled and under software control. |
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FOSC = EC |
0xFE |
EC oscillator, CLKO function on OSC2. |
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FOSC = ECPLL |
0xFF |
EC oscillator, PLL enabled and under software control, CLKO function on OSC2. |
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FOSC2 -- Default/Reset System Clock Select bit |
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FOSC2 = OFF |
0xFB |
INTRC enabled as system clock when OSCCON<1:0> = 00. |
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FOSC2 = ON |
0xFF |
Clock selected by FOSC as system clock is enabled when OSCCON<1:0> = 00. |
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FCMEN -- Fail-Safe Clock Monitor Enable bit |
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FCMEN = OFF |
0xBF |
Fail-Safe Clock Monitor disabled. |
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FCMEN = ON |
0xFF |
Fail-Safe Clock Monitor enabled. |
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IESO -- Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit |
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IESO = OFF |
0x7F |
Two-Speed Start-up disabled. |
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IESO = ON |
0xFF |
Two-Speed Start-up enabled. |
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CONFIG2H (address:0x007FFB, mask:0xFF) |
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WDTPS -- Watchdog Timer Postscale Select bits |
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WDTPS = 1 |
0xF0 |
1:1. |
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WDTPS = 2 |
0xF1 |
1:2. |
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WDTPS = 4 |
0xF2 |
1:4. |
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WDTPS = 8 |
0xF3 |
1:8. |
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WDTPS = 16 |
0xF4 |
1:16. |
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WDTPS = 32 |
0xF5 |
1:32. |
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WDTPS = 64 |
0xF6 |
1:64. |
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WDTPS = 128 |
0xF7 |
1:128. |
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WDTPS = 256 |
0xF8 |
1:256. |
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WDTPS = 512 |
0xF9 |
1:512. |
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WDTPS = 1024 |
0xFA |
1:1024. |
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WDTPS = 2048 |
0xFB |
1:2048. |
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WDTPS = 4096 |
0xFC |
1:4096. |
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WDTPS = 8192 |
0xFD |
1:8192. |
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WDTPS = 16384 |
0xFE |
1:16384. |
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WDTPS = 32768 |
0xFF |
1:32768. |
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CONFIG3L (address:0x007FFD, mask:0xF1) |
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CCP2MX -- CCP2 MUX bit |
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CCP2MX = ALTERNATE |
0xFE |
CCP2 is multiplexed with RB3. |
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CCP2MX = DEFAULT |
0xFF |
CCP2 is multiplexed with RC1. |
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