Performance Monitoring Events—AMD Athlon™ Processor

This section describes the performance monitoring events for 32-bit AMD Athlon™ processors. The AMD Athlon processor provides four 48-bit performance counters, which allows four types of events to be monitored simultaneously. The performance counters are not guaranteed to be fully accurate and should be used as a relative measure of performance to assist in application tuning. Unlisted event numbers are reserved and their results are undefined.

The Event Select value is used to select the event to be monitored. The Unit Mask is used to further qualify the event selected by the Event Select value. The Mask Value given here is an index and corresponds to actual 8-bit Unit Mask as specified in the following table.

Mask value Unit Mask
0 0x01
1 0x02
2 0x04
3 0x08
4 0x10
5 0x20
6 0x40
7 0x80

Execution events

Event Select C0h Retired instructions

The number of instructions retired (including exceptions, interrupts and resyncs.)

Event Select C1h Retired Ops

The number of micro-ops retired.

Event Select C2h Retired branches

The number of branch instructions retired (conditional, unconditional, exceptions, and interrupts.)

Event Select C3h Retired branches mispredicted

The number of branch instructions retired that were not correctly predicted.

Event Select C4h Retired taken branches

The number of taken branches that were retired.

Event Select C5h Retired taken branches mispredicted

The number of retired taken branches that were mispredicted.

Event Select C6h Retired far control transfers

The number of far control transfers retired.

Event Select C7h Retired resync branches

The number of retired resync branches. Only non-control transfer branches are counted.

Event Select CDh Interrupts masked cycles

The number of processor cycles where interrupts are masked (EFLAGS.IF=0.)

Event Select CEh Interrupts masked while pending cycles

The number of processor cycles where interrupts are masked (INTR while EFLAGS.IF=0) and an interrupt is pending.

Event Select Interrupts takenCFh

Number of taken hardware interrupts.

Data cache events

Event Select 40h Data cache accesses

The number of accesses to the data cache for load and store references.

Event Select 41h Data cache misses

The number of data cache references which missed in the data cache.

Event Select 42h Data cache refills from L2

The number of data cache refills satisfied from the L2 cache.

Mask value Description
0    Invalid cache state
1    Shared cache state
2    Exclusive cache state
3    Owner cache state
4    Modified cache state

Event Select 43h Data cache refills from system

The number of data cache refills satisfied from the system (including system memory.)

Mask value Description
0    Invalid cache state
1    Shared cache state
2    Exclusive cache state
3    Owner cache state
4    Modified cache state

Event Select 44h Data cache writebacks

The number of data cache writebacks (data cache lines written to the L2 cache or system memory.)

Mask value Description
0    Invalid cache state
1    Shared cache state
2    Exclusive cache state
3    Owner cache state
4    Modified cache state

Event Select 45h L1 DTLB misses and L2 DTLB hits

The number of data cache accesses that missed in the L1 DTLB and hit in the L2 DTLB.

Event Select 46h L1 and L2 DTLB misses

The number of data cache accesses that missed in both the L1 and L2 DTLBs.

Event Select 47h Misaligned data references

The number of data cache accesses that were misaligned.

Instruction cache events

Event Select 80h Instruction cache fetches

The number of instruction cache fetches.

Event Select 81h Instruction cache misses

The number of instruction fetches that missed in the instruction cache.

Event Select 84h L1 ITLB misses and L2 ITLB hits

The number of instruction fetches that miss in the L1 ITLB and hit in the L2 ITLB.

Event Select 85h L1 and L2 ITLB misses

The number of instruction fetches that miss in both the L1 and L2 ITLBs.