PIC16F18313
CONFIG1 (address:0x8007, mask:0xFFFF)
FEXTOSC -- FEXTOSC External Oscillator mode Selection bits
FEXTOSC = LP 0xFFF8 LP (crystal oscillator) optimized for 32.768 kHz; PFM set to low power.
FEXTOSC = XT 0xFFF9 XT (crystal oscillator) from 100 kHz to 4 MHz; PFM set to medium power.
FEXTOSC = HS 0xFFFA HS (crystal oscillator) above 4 MHz; PFM set to high power.
FEXTOSC = Unimplemented 0xFFFB Unimplemented.
FEXTOSC = OFF 0xFFFC Oscillator not enabled.
FEXTOSC = ECL 0xFFFD EC (external clock) below 100 kHz; PFM set to low power.
FEXTOSC = ECM 0xFFFE EC (external clock) for 100 kHz to 8 MHz; PFM set to medium power.
FEXTOSC = ECH 0xFFFF EC (external clock) above 8 MHz; PFM set to high power (device manufacturing default).
RSTOSC -- Power-up default value for COSC bits
RSTOSC = HFINT32 0xFF8F HFINTOSC with 2x PLL (32MHz).
RSTOSC = EXT4X 0xFF9F EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
RSTOSC = EXT2X 0xFFAF EXTOSC with 2x PLL, with EXTOSC operating per FEXTOSC bits.
RSTOSC = SOSC 0xFFBF SOSC (31kHz).
RSTOSC = LFINT 0xFFCF LFINTOSC (31kHz).
RSTOSC = Unimplemented 0xFFDF Unimplemented.
RSTOSC = HFINT1 0xFFEF HFINTOSC (1MHz).
RSTOSC = EXT1X 0xFFFF EXTOSC operating per FEXTOSC bits (device manufacturing default).
CLKOUTEN -- Clock Out Enable bit
CLKOUTEN = ON 0xFEFF CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
CLKOUTEN = OFF 0xFFFF CLKOUT function is disabled; I/O or oscillator function on OSC2.
CSWEN -- Clock Switch Enable bit
CSWEN = OFF 0xF7FF The NOSC and NDIV bits cannot be changed by user software.
CSWEN = ON 0xFFFF Writing to NOSC and NDIV is allowed.
FCMEN -- Fail-Safe Clock Monitor Enable
FCMEN = OFF 0xDFFF Fail-Safe Clock Monitor is disabled.
FCMEN = ON 0xFFFF Fail-Safe Clock Monitor is enabled.
CONFIG2 (address:0x8008, mask:0xFFFF)
MCLRE -- Master Clear Enable bit
MCLRE = OFF 0xFFFE MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port pin's WPU control bit.
MCLRE = ON 0xFFFF MCLR/VPP pin function is MCLR; Weak pull-up enabled .
PWRTE -- Power-up Timer Enable bit
PWRTE = ON 0xFFFD PWRT enabled.
PWRTE = OFF 0xFFFF PWRT disabled.
WDTE -- Watchdog Timer Enable bits
WDTE = OFF 0xFFF3 WDT disabled; SWDTEN is ignored.
WDTE = SWDTEN 0xFFF7 WDT controlled by the SWDTEN bit in the WDTCON register.
WDTE = SLEEP 0xFFFB WDT enabled while running and disabled while in SLEEP/IDLE; SWDTEN is ignored.
WDTE = ON 0xFFFF WDT enabled, SWDTEN is ignored.
LPBOREN -- Low-power BOR enable bit
LPBOREN = ON 0xFFDF ULPBOR enabled.
LPBOREN = OFF 0xFFFF ULPBOR disabled.
BOREN -- Brown-out Reset Enable bits
BOREN = OFF 0xFF3F Brown-out Reset disabled.
BOREN = SBOREN 0xFF7F Brown-out Reset enabled according to SBOREN.
BOREN = SLEEP 0xFFBF Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored.
BOREN = ON 0xFFFF Brown-out Reset enabled, SBOREN bit ignored.
BORV -- Brown-out Reset Voltage selection bit
BORV = HIGH 0xFDFF Brown-out voltage (Vbor) set to 2.7V.
BORV = LOW 0xFFFF Brown-out voltage (Vbor) set to 2.45V.
PPS1WAY -- PPSLOCK bit One-Way Set Enable bit
PPS1WAY = OFF 0xF7FF The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence).
PPS1WAY = ON 0xFFFF The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle.
STVREN -- Stack Overflow/Underflow Reset Enable bit
STVREN = OFF 0xEFFF Stack Overflow or Underflow will not cause a Reset.
STVREN = ON 0xFFFF Stack Overflow or Underflow will cause a Reset.
DEBUG -- Debugger enable bit
DEBUG = ON 0xDFFF Background debugger enabled.
DEBUG = OFF 0xFFFF Background debugger disabled.
CONFIG3 (address:0x8009, mask:0xFFFF)
WRT -- User NVM self-write protection bits
WRT = ALL 0xFFFC 0000h to 07FFh write protected, no addresses may be modified.
WRT = HALF 0xFFFD 0000h to 03FFh write-protected, 0400h to 07FFh may be modified.
WRT = BOOT 0xFFFE 0000h to 01FFh write-protected, 0200h to 07FFh may be modified.
WRT = OFF 0xFFFF Write protection off.
LVP -- Low Voltage Programming Enable bit
LVP = OFF 0xDFFF HV on MCLR/VPP must be used for programming.
LVP = ON 0xFFFF Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
CONFIG4 (address:0x800A, mask:0xFFFF)
CP -- User NVM Program Memory Code Protection bit
CP = ON 0xFFFE User NVM code protection enabled.
CP = OFF 0xFFFF User NVM code protection disabled.
CPD -- Data NVM Memory Code Protection bit
CPD = ON 0xFFFD Data NVM code protection enabled.
CPD = OFF 0xFFFF Data NVM code protection disabled.

This page generated automatically by the device-help.pl program (2014-05-17 13:45:45 UTC) from the 8bit_device.info file (rev: 1.19) of mpasmx and from the gputils source package (rev: svn 1017). The mpasmx is included in the MPLAB X.